Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder-Reference-Cited by-同舟云学术

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Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder

Published:2023-02-27 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)
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Author:

Garcia Bruna¹,Silveira Bianca²,Diniz Claudio³,Palomino Daniel²,Correa Guilherme²

Affiliation:

1. ViTech, UFPel,Pelotas,Brazil

2. ViTech, PPGC – UFPel,Pelotas,Brazil

3. Institute of Informatics,PGMICRO – UFRGS,Porto Alegre,Brazil

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10108078/10108098/10108348.pdf?arnumber=10108348

Reference11 articles.

1. Transform Coding in the VVC Standard

2. Lightweight Hardware Transform Design for the Versatile Video Coding 4K ASIC Decoders

3. Versatile Video Coding Standard: A Review From Coding Tools to Consumers Deployment

4. Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard

5. A 2-D Multiple Transform Processor for the Versatile Video Coding Standard

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Implementation of a Hardware Accelerated VVC Decoder on ARM and FPGA;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

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