A Real-Time FPGA Implementation of the CCSDS 123.0-B-2 Standard
Author:
Affiliation:
1. Department of Computer Architecture and Automation, Universidad Complutense, Madrid, Spain
Funder
Spanish Ministerio de Asuntos Económicos y Transformación Digital
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Earth and Planetary Sciences,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/36/9633014/09738635.pdf?arnumber=9738635
Reference25 articles.
1. An Extremely Pipelined FPGA Implementation of a Lossy Hyperspectral Image Compression Algorithm
2. Highly-Parallel GPU Architecture for Lossy Hyperspectral Image Compression
3. SHyLoC 2.0: A Versatile Hardware Solution for On-Board Data and Hyperspectral Image Compression on Future Space Missions
4. A 3.3 Gbps CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA
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2. Leveraging Seed Generation for Efficient Hardware Acceleration of Lossless Compression of Remotely Sensed Hyperspectral Images;Electronics;2024-06-01
3. Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital;Microprocessors and Microsystems;2024-03
4. Removing Data Dependencies in the CCSDS 123.0-B-2 Predictor Weight Updating;IEEE Geoscience and Remote Sensing Letters;2024
5. Protecting the Ccsds 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications;2024
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