1. Impact of snapback behavior on system level ESD performance with single and double stack of bipolar ESD structures;laine;Proc Elect Overstress/Electrostatic Discharge Symp,2012
2. System failures due to an induced ESD within the system;isofuku;Proc Elect Overstress/Electrostatic Discharge Symp,2012
3. A flexible simulation model for system level ESD stresses with application to ESD design and troubleshooting;mertens;Proc Elect Overstress/Electrostatic Discharge Symp,2012
4. IEC system level ESD challenges and effective protection strategy for USB2 interface;bertonnaud;Proc Elect Overstress/Electrostatic Discharge Symp,2012
5. A design strategy for 8 kV/contact 15 kV/air gap IEC 61000-4-2 robustness without on board suppressors;gallerano;Proc Elect Overstress/Electrostatic Discharge Symp,2012