Evaluation of Statistical Fault Analysis Using Input Timing Violation of Sequential Circuit on Cryptographic Module Under IEMI
Author:
Affiliation:
1. Nara Institute of Science and Technology, Ikoma, Japan
2. Department of Informatics, University of Electro Communications, Tokyo, Japan
Funder
JSPS KAKENHI
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics
Link
http://xplorestaging.ieee.org/ielx7/15/10046174/09932280.pdf?arnumber=9932280
Reference20 articles.
1. Study on the effect of clock rise time on fault occurrence under IEMI
2. Investigation in burst pulse injection method for fault based cryptanalysis
3. Fault Attacks on AES with Faulty Ciphertexts Only
4. Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits
5. WDDL is Protected against Setup Time Violation Attacks
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