Page-Address Coalescing of Vector Gather Instructions for Efficient Address Translation
Author:
Affiliation:
1. Graduate School of Information Sciences, Tohoku University,Sendai,Japan
2. Tohoku University,Cyberscience Center,Sendai,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10027178/10027180/10027181.pdf?arnumber=10027181
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3. Vector engine processor of NEC's brand-new supercomputer SX-Aurora TSUBASA;yamada;Intenational symposium on High Performance Chips (Hot Chips 2018),2018
4. Developing an Efficient Vector-Friendly Implementation of the Breadth-First Search Algorithm for NEC SX-Aurora TSUBASA
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