Design and Analysis of Gate-Stack 7 nm node Tri-gate FinFET for low power Application
Author:
Affiliation:
1. OUTR,Electronics and Instrumentation Engg.,Bhubaneswar,India
2. PMEC,Electronics and Tele-Communication Engg.,Berhampur,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10291170/10291178/10291277.pdf?arnumber=10291277
Reference8 articles.
1. Scaling Limits of Rectangular and Trapezoidal Channel FinFETs;mohseni;IEEE Green Technologies Conference,2013
2. Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)
3. Analog/RF performance analysis of channel engineered high- K gate-stack based junctionless Trigate-FinFET
4. Design and Analysis of Gate Stack Silicon-on-Insulator Nanosheet FET for Low Power Applications;yuvaraj;Silicon,2021
5. Scaling of Trigate nanowire (NW) MOSFETs to sub-7nm width: 300K transition to Single Electron Transistor
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