Interface-trap modeling for silicon-nanowire MOSFETs
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5482567/5488659/05488693.pdf?arnumber=5488693
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Electrical Stress on the CMOS Inverters Made by Junctionless Gate-All-Around Transistors;IEEE Transactions on Electron Devices;2024-05
2. Compact Modeling of Schottky Gate-all-around Silicon Nanowire Transistors with Halo Doping;Silicon;2021-01-25
3. Surface Trap-Induced Conductivity Type Switching in Semiconductor Nanowires: Analytical and Numerical Analyses;IEEE Transactions on Electron Devices;2017-12
4. Oxide thickness dependent compact model of channel noise for E-mode AlGaN/GaN MOS-HEMT;AEU - International Journal of Electronics and Communications;2017-12
5. Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs;Semiconductor Science and Technology;2016-09-13
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