Improving trace cache effectiveness with branch promotion and trace packing-Reference-Cited by-同舟云学术

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Improving trace cache effectiveness with branch promotion and trace packing

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Container-title:Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235)
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Author:

Patel S.J.,Evers M.,Patt Y.N.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx4/5642/15122/00694786.pdf?arnumber=694786

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming;IEEE Transactions on Computers;2019-12-01

3. A Survey on Thread-Level Speculation Techniques;ACM Computing Surveys;2016-11-11

4. Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?;Architecture of Computing Systems - ARCS 2006;2006

5. Path-based next N trace prefetch in trace processors;Microprocessors and Microsystems;2005-08

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