A 90.9% Efficient 4-phase Interleaved Charge Pump Topology with FBB and Internal Clock Boosting Technique for Energy Harvesting Applications
Author:
Affiliation:
1. Mindanao State University-Iligan Institute of technology,Microelectronics Laboratory,Department of Electrical Engineering and Technology,Iligan City,Philippines
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9977436/9977454/09977687.pdf?arnumber=9977687
Reference14 articles.
1. An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process
2. A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start
3. A low ripple CMOS charge Pump for low-voltage application
4. CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction
5. Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process
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1. 4-Phase Interleaved Charge Pump Topologies with Reversion Loss Elimination Techniques for IoT Applications;2023 22nd International Symposium on Communications and Information Technologies (ISCIT);2023-10-16
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