Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects-Reference-Cited by-同舟云学术

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Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects

Published:2008-04 Issue: Volume: Page:
ISSN:
Container-title:Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
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Author:

Goossens Kees,Bennebroek Martijn,Hur Jae Young,Wahlah Muhammad Aqeel

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4492707/4492708/04492724.pdf?arnumber=4492724

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Hybrid Prototyping for Manycore Design and Validation;Lecture Notes in Computer Science;2019

2. Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources;Integration;2018-09

3. On-Chip Networks, Second Edition;Synthesis Lectures on Computer Architecture;2017-06-17

4. Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-01

5. Real Time FPGA Communication System Using Ethernet for Robotics;Procedia Computer Science;2015

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