Packet Header Classification for Network Intrusion Detection System Based on FPGA-Reference-Cited by-同舟云学术

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Packet Header Classification for Network Intrusion Detection System Based on FPGA

Published:2022-06-09 Issue: Volume: Page:
ISSN:
Container-title:2022 International Congress on Human-Computer Interaction, Optimization and Robotic Applications (HORA)
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Author:

Dakhil Yousif Hosain¹,Ozbek Mehmet Efe²,Al-Kaseem Bilal R.³

Affiliation:

1. College of Engineering, Atilim University,Department of Information Technology Engineering,Istanbul,Turkey

2. College of Engineering, Atilim University,Department of Electrical and Electronics Engineering,Istanbul,Turkey

3. College of Engineering, Al-Iraqia University,Department of Electrical Engineering,Baghdad,Iraq

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9799780/9799803/09800025.pdf?arnumber=9800025

Reference15 articles.

1. FPGA Based Packet Classification Using Multi-Pipeline Architecture

2. Design and Implementation of Efficient Packet Classification on FPGA for NoC Based Designs;r d;International Journal of Engineering Research & Technology,2015

3. Design of High Performance Packet Classification Architecture for Communication Networks;khan;Journal of Telecommunication Electronic and Computer Engineering,2017

4. Problems of increasing ef-ficiency of NIDS by using implementing methods packet classifications on FPGA;karimov;2019 International Conference on Information Science and Communication Technology (ICISCT),0

5. Hardware-Assisted Flow Monitoring for High Speed Networks

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