Author:
Rao Pachara V.,Raj Cyril Prasanna
Cited by
8 articles.
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1. Low Power Multiplier Using Approximate Adder for Error Tolerant Applications;IETE Journal of Research;2024-09-11
2. Design of DADDA Multiplier Using High Performance and Low Power Full Adder;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
3. Design of Wallace tree multiplier circuit using high performance and low power full adder;E3S Web of Conferences;2023
4. VLSI Design and Implementation of Multipliers for DSP Applications;International Journal of Advanced Research in Science, Communication and Technology;2022-05-15
5. 8-Bit Modified Booth Multiplier using 20nm FinFET Technology;2022 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2022-02-19