Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator

Author:

Zhang Jeff Jun,Gu Tianyu,Basu Kanad,Garg Siddharth

Publisher

IEEE

Cited by 69 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning;2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS);2024-07-03

2. Design Exploration of Fault-Tolerant Deep Neural Networks Using Posit Number Representation System;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07

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4. Approximate Fault-Tolerant Neural Network Systems;2024 IEEE European Test Symposium (ETS);2024-05-20

5. Highly Fault-Tolerant Systolic-Array-Based Matrix Multiplication;Electronics;2024-05-05

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