MR-PIPA: An Integrated Multilevel RRAM (HfO<sub> <i>x</i> </sub>)-Based Processing-In-Pixel Accelerator-Reference-Cited by-同舟云学术

MR-PIPA: An Integrated Multilevel RRAM (HfO_x)-Based Processing-In-Pixel Accelerator

Published:2022-12 Issue:2 Volume:8 Page:59-67
ISSN:2329-9231
Container-title:IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
language:
Short-container-title:IEEE J. Explor. Solid-State Comput. Devices Circuits

Author:

Abedin Minhaz¹,Roohi Arman²^ORCID,Liehr Maximilian¹,Cady Nathaniel¹^ORCID,Angizi Shaahin³^ORCID

Affiliation:

1. College of Nanoscale Science and Engineering, SUNY Polytechnic Institute, Albany, NY, USA

2. School of Computing, University of Nebraska–Lincoln, Lincoln, NE, USA

3. Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electronic, Optical and Magnetic Materials

Link

Reference32 articles.

1. PISA: A binary-weight processing-in-sensor accelerator for edge image processing;angizi;arXiv 2202 09035,2022

2. Reading digits in natural images with unsupervised feature learning;netzer;Proc NIPS,2011

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