A Novel SuperSteep Subthreshold Slope Dual-Channel FET Utilizing a Gate-Controlled Thyristor Mode-Induced Positive Feedback Current
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/7862872/07845565.pdf?arnumber=7845565
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 3D Stackable DRAM: Capacitor-less Three-Wordline Gate-Controlled Thyristor (GCT) RAM with >40 μ A Current Sensing Window, >1010 Endurance, and 3-second Retention at Room Temperature;2022 International Electron Devices Meeting (IEDM);2022-12-03
2. NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors;Scientific Reports;2022-03-07
3. Inverter design with positive feedback field-effect transistors;Semiconductor Science and Technology;2022-01-28
4. Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors;Nanotechnology;2021-03-09
5. More physical understanding of current characteristics of tunneling field-effect transistor leveraged by gate positions and properties through dual-gate and gate-all-around structuring;Applied Physics A;2020-10-07
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