An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach
Author:
Funder
JSPS KAKENHI
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science
Link
http://xplorestaging.ieee.org/ielx7/6287639/9312710/09309221.pdf?arnumber=9309221
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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2. AIMC Modeling and Parameter Tuning for Layer-Wise Optimal Operating Point in DNN Inference;IEEE Access;2023
3. A Spiking Neural Network with Resistively Coupled Synapses Using Time-to-First-Spike Coding Towards Efficient Charge-Domain Computing;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
4. HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs;IEEE Journal of Solid-State Circuits;2022-04
5. Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS;IEEE Access;2022
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