Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter-Reference-Cited by-同舟云学术

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Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter

Published:2019 Issue: Volume:7 Page:97719-97731
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Kumar Kanike Vinod^ORCID,Kumar R. Saravana

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/8600701/08766796.pdf?arnumber=8766796

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2. OSG-PLL-based method of a solar PV grid-interfaced transformer-less cascaded H-bridge multilevel inverter for power quality enhancement;Electrical Engineering;2024-05-22

3. Design and Implementation of Multilevel Inverter Topology with Reduced Switching Components;Proceedings of the Bulgarian Academy of Sciences;2024-01-29

4. Performance Evaluation of a 17-Level Octuple Boost Inverter for a Grid-Connected PV System;IEEE Access;2024

5. A Three-Phase Hybrid Multilevel Inverter for Medium Voltage Applications;2023 3rd International Conference on Emerging Smart Technologies and Applications (eSmarTA);2023-10-10

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