Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM-Reference-Cited by-同舟云学术

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Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

Published:2020 Issue: Volume:8 Page:59290-59304
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Korikawa Tomohiro^ORCID,Kawabata Akio^ORCID,He Fujun^ORCID,Oki Eiji^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/8948470/09039620.pdf?arnumber=9039620

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Design Space Exploration and Evaluation for Main-Memory Hash Joins in Storage Class Memory;Proceedings of the VLDB Endowment;2023-02

2. Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies;IEEE Access;2022

3. Memory Network Architecture for Packet Processing in Functions Virtualization;2021 IEEE 7th International Conference on Network Softwarization (NetSoft);2021-06-28

4. Unavailability-Aware Shared Virtual Backup Allocation for Middleboxes: A Queueing Approach;IEEE Transactions on Network and Service Management;2021-06

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