Efficient and Scalable Architecture for Multiple-Chip Implementation of Simulated Bifurcation Machines
Author:
Affiliation:
1. Corporate Research and Development Center, Toshiba Corporation, Kawasaki, Saiwai-ku, Japan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/6287639/10380310/10460551.pdf?arnumber=10460551
Reference45 articles.
1. A Currency Arbitrage Machine Based on the Simulated Bifurcation Algorithm for Ultrafast Detection of Optimal Opportunity
2. Correlation-Diversified Portfolio Construction by Finding Maximum Independent Set in Large-Scale Market Graph
3. Pilot Allocation Optimization using Digital Annealer for Multi-cell Massive MIMO
4. High-Speed Resource Allocation Algorithm Using a Coherent Ising Machine for NOMA Systems
5. Efficient Migration to the Next Generation of Networks Based on Digital Annealing
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