Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability-Reference-Cited by-同舟云学术

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Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability

Published:2019 Issue: Volume:7 Page:53188-53201
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Waidyasooriya Hasitha Muthumala^ORCID,Hariyama Masanori

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/8600701/08689014.pdf?arnumber=8689014

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. FPGA-Based Acceleration of Polar-Format Algorithm for Video Synthetic-Aperture Radar Imaging;Electronics;2024-06-19

2. HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator;2024 IEEE International Conference on Consumer Electronics (ICCE);2024-01-06

3. Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2023-11-29

4. UWOmp_pro: UWOmp++ with Point-to-Point Synchronization, Reduction and Schedules;2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT);2023-10-21

5. Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes;Proceedings of the Platform for Advanced Scientific Computing Conference;2023-06-26

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