High-Throughput Deblocking Filter Architecture Using Quad Parallel Edge Filter for H.264 Video Coding Systems
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science
Link
http://xplorestaging.ieee.org/ielx7/6287639/8600701/08768053.pdf?arnumber=8768053
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Methods to develop high throughput hardware architectures for HEVC Deblocking Filter using mixed pipelined-block processing techniques;Microelectronics Journal;2022-05
2. A fast integrated deblocking filter and sample-adaptive-offset parameter estimation architecture for HEVC;Microprocessors and Microsystems;2021-09
3. Hardware Accelerator for Dual Standard Deblocking Filter;2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID);2021-02
4. A Low-Complex Frame Rate Up-Conversion with Edge-Preserved Filtering;Electronics;2020-01-15
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