An Error Bound Particle Swarm Optimization for Analog Circuit Sizing-Reference-Cited by-同舟云学术

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An Error Bound Particle Swarm Optimization for Analog Circuit Sizing

Published:2024 Issue: Volume:12 Page:50126-50136
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Shreeharsha K. G.¹^ORCID,Siddharth R. K.²,Vasantha M. H.³,Kumar Y. B. Nithin³^ORCID

Affiliation:

1. Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal, Karnataka, India

2. Department of Mechatronics Engineering, Parul Institute of Technology, Parul University, Vadodara, India

3. Department of Electronics and Communication Engineering, National Institute of Technology Goa, Goa, India

Funder

Research and Development Project through the Department of Science and Technology-Science and Engineering Research Board (DST-SERB), Scheme of Government of India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/6287639/10380310/10493039.pdf?arnumber=10493039

Reference39 articles.

1. Parameter Optimization of Differential Evolution and Particle Swarm Optimization in the Context of Optimal Power Flow

2. Evolutionary Heuristic A* Search: Heuristic Function Optimization via Genetic Algorithm

3. Evolving Initial Heuristic Functions for Agent-Centered Heuristic Search

4. A Cooperative Coevolution Hyper-Heuristic Framework for Workflow Scheduling Problem

5. Heuristic and Backtracking Algorithms for Improving the Performance of Efficiency Analysis Trees

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