High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs-Reference-Cited by-同舟云学术

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High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

Published:2021 Issue: Volume:9 Page:54286-54297
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Tariq Osama Bin^ORCID,Shan Junnan^ORCID,Floros Georgios,Sotiriou Christos P.^ORCID,Casu Mario R.^ORCID,Lazarescu Mihai Teodor^ORCID,Lavagno Luciano^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/9312710/09381853.pdf?arnumber=9381853

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2024-08-05

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3. A Novel Real-Time Processing Wideband Waveform Generator of Airborne Synthetic Aperture Radar;Remote Sensing;2024-01-27

4. FPGA Implementation of Robust and Secure Transmission Cryptosystem for Satellite Images;IEEE Access;2024

5. Design of real-time object classification acceleration platform based on SDSoC;Fourth International Conference on Computer Science and Communication Technology (ICCSCT 2023);2023-10-11

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