A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection-Reference-Cited by-同舟云学术

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A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

Published:2022 Issue: Volume:10 Page:126429-126439
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Chen Poki¹^ORCID,Wijaya Joshua Adiel¹^ORCID,Kajihara Seiji²,Adiono Trio³^ORCID,Chen Hsiang-Yu¹,Wang Ruei-Ting¹,Miyake Yousuke²^ORCID

Affiliation:

1. Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan

2. Kyushu Institute of Technology, Fukuoka, Japan

3. School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Bandung, Indonesia

Funder

Ministry of Science and Technology

National Taiwan University of Science and Technology, Kyushu Institute of Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09967976.pdf?arnumber=9967976

Reference39 articles.

1. A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

2. Design and Characterization of a Low-Cost FPGA-Based TDC

3. All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of $-{\hbox {0.7}} ~^{\circ}{\hbox {C}}-+{\hbox {0.6}}~^{\circ}{\hbox {C}}$ After One-Point Calibration

4. An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking

5. A high resolution FPGA-based merged delay line TDC with nonlinearity calibration;chen;Proc IEEE Int Symp Circuits Syst (ISCAS),2013

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