Lightweight and Low-Latency AES Accelerator Using Shared SRAM-Reference-Cited by-同舟云学术

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Lightweight and Low-Latency AES Accelerator Using Shared SRAM

Published:2022 Issue: Volume:10 Page:30457-30464
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Lee Jae Seong¹^ORCID,Choi Piljoo²^ORCID,Kim Dong Kyue³^ORCID

Affiliation:

1. Department of Electronics and Computer Engineering, Hanyang University, Seoul, South Korea

2. Department of Computer Engineering, Pukyong National University, Busan, South Korea

3. Department of Electronic Engineering, Hanyang University, Seoul, South Korea

Funder

Institute of Information & Communications Technology Planning & Evaluation (IITP) Grant

Korea Government (MSIT)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09726196.pdf?arnumber=9726196

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Novel High Throughput-to-Area Efficiency and Strong-Resilience Datapath of AES for Lightweight Implementation in IoT Devices;IEEE Internet of Things Journal;2024-05-15

2. Lightweight Polynomial Multiplication Accelerator for NTRU Using Shared SRAM;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-12

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