A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices-Reference-Cited by-同舟云学术

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A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices

Published:2023 Issue: Volume:11 Page:61422-61436
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Elbediwy Mostafa¹^ORCID,Pontikakis Bill¹^ORCID,David Jean-Pierre¹^ORCID,Savaria Yvon¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Polytechnique Montréal, Montreal, QC, Canada

Funder

Kaloom, Intel, Noviflow, Prompt Quebec

Natural Sciences and Engineering Research Council of Canada

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/10005208/10153594.pdf?arnumber=10153594

Reference33 articles.

1. Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis

2. An Exhaustive Survey on P4 Programmable Data Plane Switches: Taxonomy, Applications, Challenges, and Future Trends

3. Towards Programmable Packet Scheduling

4. A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking

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