Design and Experimentation of a Single-Phase PLL With Novel OSG Method
Author:
Affiliation:
1. Department of Industrial Engineering, University of Padova, Padova, Italy
Funder
ENEA Agenzia nazionale per le nuove tecnologie, l’energia e lo sviluppo economico sostenibile
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science
Link
http://xplorestaging.ieee.org/ielx7/6287639/9668973/09740183.pdf?arnumber=9740183
Reference33 articles.
1. Fast and robust software‐based digital phase‐locked loop for power electronics applications
2. DC Offset Error Compensation for Synchronous Reference Frame PLL in Single-Phase Grid-Connected Converters
3. Optimizing of sampling in a low-cost single-phase instantaneous AC-grid synchronization unit with discrete calculation of derivative function
4. A Three-Phase Frequency-Adaptive Phase-Locked Loop for Independent Single-Phase Operation
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