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A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator

  • Published:2022 Issue: Volume:10 Page:11830-11845
  • ISSN:2169-3536
  • Container-title:IEEE Access
  • language:
  • Short-container-title:IEEE Access

Author:

Pham Hoai LuanORCID,Tran Thi HongORCID,Duong Le Vu TrungORCID,Nakashima YasuhikoORCID

Funder

Japan Science and Technology Agency (JST) under a Strategic Basic Research Programs Precursory Research for Embryonic Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

2. Revised elliptic curve cryptography multi-signature scheme (RECC-MSS) for enhancing security in electronic health record (EHR) system;Journal of Intelligent & Fuzzy Systems;2023-12-02

3. Efficient and High-Speed CGRA Accelerator for Cryptographic Applications;2023 Eleventh International Symposium on Computing and Networking (CANDAR);2023-11-28

4. Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design;Pertanika Journal of Science and Technology;2023-11-06

5. Design and Implementation of AES-SHA Security Hardware using FPGA;2023 First International Conference on Advances in Electrical, Electronics and Computational Intelligence (ICAEECI);2023-10-19
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