FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio-Reference-Cited by-同舟云学术

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FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

Published:2022 Issue: Volume:10 Page:119386-119401
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Shah Nasir Ali¹^ORCID,Lazarescu Mihai T.¹^ORCID,Quasso Roberto²^ORCID,Scarpina Salvatore³^ORCID,Lavagno Luciano¹^ORCID

Affiliation:

1. Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy

2. Innovation Department, Telecom Italia, Rome, Italy

3. Digital & Advanced Technologies, IVECO S.p.A., Turin, Italy

Funder

Innovation Department, TIM S.p.A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09944632.pdf?arnumber=9944632

Reference54 articles.

1. From opencl to high-performance hardware on FPGAS

2. DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler

3. High-Level Synthesis for FPGAs: From Prototyping to Deployment

4. 3GPP 3D MIMO channel model: a holistic implementation guideline for open source simulation tools

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. CUDA-Optimized GPU Acceleration of 3GPP 3D Channel Model Simulations for 5G Network Planning;Electronics;2023-07-25

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