Novel Dual Work Function Buried Channel Array Transistor Process Design for Sub-17 nm DRAM-Reference-Cited by-同舟云学术

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Novel Dual Work Function Buried Channel Array Transistor Process Design for Sub-17 nm DRAM

Published:2024 Issue: Volume:12 Page:63049-63065
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Park Dong-Sik¹^ORCID,Im Dong-Hyun²,Kim Yun-Jung²,Sam Lee Sung²,Kang Byung-Jae²,Seo Jae-Hong²,Koo Taewoong²,Choi Byoungdeog³^ORCID

Affiliation:

1. Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, Republic of Korea

2. DRAM Process Architecture Team, Samsung Electronics Company, Hwasung, Republic of Korea

3. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Republic of Korea

Funder

Samsung Electronics Company Ltd

Sungkyunkwan University and the BK21 FOUR(Graduate School Innovation) funded by the Ministry of Education (MOE), South Korea

National Research Foundation of Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/6287639/10380310/10453579.pdf?arnumber=10453579

Reference15 articles.

1. 1T-1C Dynamic Random Access Memory Status, Challenges, and Prospects

2. 20 nm DRAM: A new beginning of another revolution;Park;IEDM Tech. Dig.,2015

3. Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time

4. The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond

5. S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

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