A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications-Reference-Cited by-同舟云学术

A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

Published:2022 Issue: Volume:10 Page:62471-62483
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Heo Minuk¹,Bae Sunghyun¹,Lee Ja-Yol²^ORCID,Kim Cheonsu²,Lee Minjae¹^ORCID

Affiliation:

1. School of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Buk-gu, Gwangju, South Korea

2. Electronics and Telecommunications Research Institute, Yuseong-gu, Daejeon, South Korea

Funder

Institute of Information and Communications Technology Planning and Evaluation (IITP) grant through the Ministry of Science and ICT (MSIT), South Korea, [Development on Multibeam Antenna Technology]

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09794638.pdf?arnumber=9794638

Reference47 articles.

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2. Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

3. A bang bang phase-locked loop using automatic loop gain control and loop latency reduction techniques;kuan;IEEE J Solid-State Circuits,2016

4. A Loop Gain Optimization Technique for Integer-$N$ TDC-Based Phase-Locked Loops

5. Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs

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