A 22-Bit 34-uW Sturdy-MASH Digital Delta-Sigma Modulator with Nested Bus-Splitting and Resolution Enhancement-Reference-Cited by-同舟云学术

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A 22-Bit 34-uW Sturdy-MASH Digital Delta-Sigma Modulator with Nested Bus-Splitting and Resolution Enhancement

Published:2023-10-27 Issue: Volume: Page:
ISSN:
Container-title:2023 5th International Conference on Circuits and Systems (ICCS)
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Author:

Zhang Zhe¹,Xing Xinpeng²,Ren Siming³,Feng Haigang¹,Wang Han⁴,Yang Lei⁴

Affiliation:

1. Shenzhen International Graduate School, Tsinghua University,Shenzhen,China

2. School of Integrated Circuits, SUN YAT-SEN University,Shenzhen,China

3. The University of Hong Kong,Faculty of Social Sciences,Hongkong,China

4. Megahunt Technologies Inc.,Analog Design Department,Beijing,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10367210/10367213/10367236.pdf?arnumber=10367236

Reference8 articles.

1. Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input

2. Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM

3. Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

4. A high-throughput spur-free hybrid nested bus-splitting/HK-MASH digital delta-sigma modulator

5. Maximum Sequence Length MASH Digital Delta–Sigma Modulators

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