A Fractional-N Synthesizer Based on Programmable Frequency Multiplier for 5G+ Communication System
Author:
Affiliation:
1. UCT Laboratory, Kookmin University, Seoul, South Korea
Funder
Institute of Information and Communications Technology Planning and Evaluation
Korea Government [Ministry of Science and ICT (MSIT)]
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Radiation
Link
http://xplorestaging.ieee.org/ielx7/22/10091956/09965581.pdf?arnumber=9965581
Reference37 articles.
1. Sub-Sampling PLL For Millimeter Wave Applications: An Overview
2. Analysis of Phase Noise in Phase/Frequency Detectors
3. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$
4. A 16-Times Frequency Multiplier for 5G Synthesizer
5. A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis
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1. Mathematical modelling and research of output spectrum of synthesizers based on high-speed DAC for 5G;Journal of Physics: Conference Series;2023-09-01
2. High-speed digital-to-analogue converters phase noise modelling;Journal of Physics: Conference Series;2023-09-01
3. Study on Spurious Suppression Behavior of Fractional-N and DDS Based PLL Synthesizers with Fine Frequency Resolution;2023 International Conference on Microwave and Millimeter Wave Technology (ICMMT);2023-05-14
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