Characterization and Modeling of 1/$f$ Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides-Reference-Cited by-同舟云学术

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Characterization and Modeling of 1/$f$ Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

Published:2011-05 Issue:3 Volume:10 Page:417-423
ISSN:1536-125X
Container-title:IEEE Transactions on Nanotechnology
language:
Short-container-title:IEEE Trans. Nanotechnology

Author:

Baek Rock-Hyun,Baek Chang-Ki,Choi Hyun-Sik,Lee Jeong-Soo,Yeoh Yun Young,Yeo Kyoung Hwan,Kim Dong-Won,Kim Kinam,Kim Dae M.,Jeong Yoon-Ha

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://xplorestaging.ieee.org/ielx5/7729/5764947/05422646.pdf?arnumber=5422646

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs;Solid-State Electronics;2022-03

2. Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs;Solid-State Electronics;2021-10

3. Low-Frequency Noise Assessment of Vertically Stacked Si n-Channel Nanosheet FETs With Different Metal Gates;IEEE Transactions on Electron Devices;2020-11

4. Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?;2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS);2020-09-01

5. Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording;Sensors;2017-03-28

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