Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC
Author:
Affiliation:
1. Tsinghua University,Department of Electronic Engineering,Beijing,China
2. Institute of Microelectronics of the Chinese Academy of Sciences,Beijing,China
Funder
National Key Research and Development Program
NSFC
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9712466/9712479/09712556.pdf?arnumber=9712556
Reference20 articles.
1. Sparse ReRAM engine
2. Exploring the Granularity of Sparsity in Convolutional Neural Networks
3. 14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse
4. 15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating
5. 33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing
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1. Memristor Based Mixed-Accuracy Computation-in-Memory System;2023 International Conference on IC Design and Technology (ICICDT);2023-09-25
2. RAP-CIM: Reliable Time Accumulation and Efficient Pipeline Computing in Memory with Spintronics for Neural Networks;2023 IEEE 23rd International Conference on Nanotechnology (NANO);2023-07-02
3. Weight and Multiply-Accumulation Sparsity-Aware Non-Volatile Computing-in-Memory System;IEEE Transactions on Circuits and Systems II: Express Briefs;2023
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