Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx5/10208/34596/01650108.pdf?arnumber=1650108
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1. Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips;IEEE Transactions on Sustainable Computing;2023-01-01
2. A Segmented Adaptive Router for Near Energy-Proportional Networks-on-Chip;ACM Transactions on Embedded Computing Systems;2022-07-31
3. Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energy-Efficient Computing Systems;IEEE Access;2022
4. An Energy-Efficient Network-on-Chip Design using Reinforcement Learning;Proceedings of the 56th Annual Design Automation Conference 2019;2019-06-02
5. LEAD;Proceedings of the 55th Annual Design Automation Conference;2018-06-24
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