High-Speed Architecture for Successive Cancellation Decoder With Split-g Node Block
Author:
Funder
Visvesvaraya Ph.D. Scheme
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Computer Science,Control and Systems Engineering
Link
http://xplorestaging.ieee.org/ielx7/4563995/9524350/09184828.pdf?arnumber=9184828
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