A Noise-Cancelling Self-Interference Canceller with +7 dBm Self-Interference Power Handling in 0.18μ m CMOS
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9489353/9490399/09490418.pdf?arnumber=9490418
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-09
2. A Low-Noise Dual-Path Self-Interference Cancellation Architecture for Watt-Level TX Power Handling in Simultaneous Transmit and Receive;IEEE Journal of Solid-State Circuits;2024-05
3. A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression;IEEE Journal of Solid-State Circuits;2024-04
4. Single Antenna and No Circulator Full-Duplex With 52 dB Wideband Self-Interference Suppression;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-09
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