KaratSaber: New Speed Records for Saber Polynomial Multiplication using Efficient Karatsuba FPGA Architecture-Reference-Cited by-同舟云学术

KaratSaber: New Speed Records for Saber Polynomial Multiplication using Efficient Karatsuba FPGA Architecture

Author:

Wong Zheng-Yan¹,Wong Denis C.-K.²^ORCID,Lee Wai-Kong³^ORCID,Mok Kai-Ming¹,Yap Wun-She²^ORCID,Khalid Ayesha⁴^ORCID

Affiliation:

1. Faculty of Information & Communnication Technology, Universiti Tunku Abdul Rahman, Kampar, Malaysia

2. Lee Kong Chian Faculty of Engineering & Science, Universiti Tunku Abdul Rahman, Sg Long, Malaysia

3. School of Computer Engineering, Gachon University, South Korea

4. The Institute of Electronics, Communications and Information Technology (ECIT), Queen's University Belfast, U.K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

Reference26 articles.

3. Lightweight hardware implementation of R-LWE lattice-based cryptography;fan;Proc IEEE Asia Pacific Conf Circuits Syst,2019

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3. FPGA Based Accelerator for Implementation of Large Integer Polynomials;International Journal of Innovative Science and Research Technology (IJISRT);2024-05-21