Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

Author:

Josipovic Lana,Guerrieri Andrea,Ienne Paolo

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Science Applications

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

2. Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04

3. Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04

4. High-Level Synthesis;FPGA EDA;2024

5. Resource Sharing in Dataflow Circuits;ACM Transactions on Reconfigurable Technology and Systems;2023-09

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