Digital Twin for Gate-Resistor Optimization of Parallel, 100 V, 7 mΩ, GaN HEMTs based on Comprehensive Multi-Domain Simulations and Physically-Motivated Transistor Models
Author:
Affiliation:
1. University of Stuttgart,Institute of Robust Power Semiconductor Systems,Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10412244/10412389/10412580.pdf?arnumber=10412580
Reference23 articles.
1. PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
2. Thermal Boundary Analysis for High-Power-Density GaN-Based Chargers
3. Thermal study on leadframe dimensioning for high power dissipation and low inductance commutation cells;Weimer
4. Miniaturization and Thermal Design of a 170 W AC/DC Battery Charger Utilizing GaN Power Devices
5. Optimal Level Number and Performance Evaluation of Si/GaN Multi-Level Flying Capacitor Inverter for Variable Speed Drive Systems
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