Improving the Efficiency of Cryptography Algorithms on Resource-Constrained Embedded Systems via RISC-V Instruction Set Extensions
Author:
Affiliation:
1. School of Technology, Pontifical Catholic University of Rio Grande do Sul- PUCRS - Porto Alegre,Brazil
Funder
CNPq
FAPERGS
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10261937/10261649/10261964.pdf?arnumber=10261964
Reference19 articles.
1. The design of scalar AES Instruction Set Extensions for RISC-V
2. TinyCrypt Cryptographic Library;Intel,2017
3. Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms;ni?anc?;Cryptography,2022
4. OpenTitan project;lowRISC·lowRISC,2017
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1. Low-Power Magnetic Displacement Sensor Based on RISC-V Embedded System;Sensors;2024-06-29
2. Hardware Acceleration of Authenticated Encryption with Associated Data via RISC-V Instruction Set Extensions in Low Power Embedded Systems;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27
3. Hardware Acceleration of Crystals-Kyber in Low-Complexity Embedded Systems With RISC-V Instruction Set Extensions;IEEE Access;2024
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