A Low-Noise Analog Frontend with Large PD Capacitance Tolerance in 65-nm CMOS for Optical Receivers-Reference-Cited by-同舟云学术

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A Low-Noise Analog Frontend with Large PD Capacitance Tolerance in 65-nm CMOS for Optical Receivers

Published:2021-11-24 Issue: Volume: Page:
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Container-title:2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
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Author:

Wang Jingbo,Wang Tonghui,Yang Xiao,Zhang Hong

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9661584/9661598/09661603.pdf?arnumber=9661603

Reference5 articles.

1. Broadband Circuits for Optical Fiber Communication

2. A Low-Noise Design Technique for High-Speed CMOS Optical Receivers

3. Analysis of the Bridged T-Coil Circuit Using the Extra-Element Theorem

4. A 90 nm CMOS 16 Gb/s transceiver for optical interconnects;palermo;IEEE ISSCC,2007

5. A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS

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1. A Broad-Bandwidth Cascode-Feedback Transimpedance Amplifier for Short-Range Optical Communication;2023 5th International Conference on Circuits and Systems (ICCS);2023-10-27

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