Hardware Resource and Computational Density Efficient CNN Accelerator Design Based on FPGA
Author:
Funder
Research and Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9661584/9661598/09661886.pdf?arnumber=9661886
Reference8 articles.
1. Parallel dot-products for deep learning on FPGA
2. Reconfigurable pipelined 2-D convolvers for fast digital signal processing
3. Very deep convolutional networks for large-scale image recognition;simonyan,2014
4. Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference
5. Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
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4. Design and Implementation of Reconfigurable Array Structure for Convolutional Neural Network Supporting Data Reuse;2022 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC);2022-11-07
5. A General-Purpose CNN Accelerator Based on Improved Systolic Array for FPGAs;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28
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