The Design Process for Google's Training Chips: TPUv2 and TPUv3-Reference-Cited by-同舟云学术

The Design Process for Google's Training Chips: TPUv2 and TPUv3

Published:2021-03-01 Issue:2 Volume:41 Page:56-63
ISSN:0272-1732
Container-title:IEEE Micro
language:
Short-container-title:IEEE Micro

Author:

Norrie Thomas^ORCID,Patil Nishant^ORCID,Yoon Doe Hyun^ORCID,Kurian George^ORCID,Li Sheng^ORCID,Laudon James^ORCID,Young Cliff^ORCID,Jouppi Norman^ORCID,Patterson David^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/40/9388768/09351692.pdf?arnumber=9351692

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