Adaptive Loop Filter Hardware Design for 4K ASIC VVC Decoders
Author:
Affiliation:
1. INSA Rennes, CNRS, IETR—UMR 6164, Univ. Rennes, Rennes, France
2. VITEC, Chatillon, France
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Media Technology
Link
http://xplorestaging.ieee.org/ielx7/30/9786721/09691469.pdf?arnumber=9691469
Reference27 articles.
1. High performance 2D transform hardware for future video coding
2. A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard
3. Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder
4. Lightweight Hardware Transform Design for the Versatile Video Coding 4K ASIC Decoders
5. VVC In-Loop Filters
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1. A fast H.266/QTMT intra coding scheme based on predictions of learned models;Journal of the Chinese Institute of Engineers;2024-07-19
2. Area-Efficient Processing Elements-Based Adaptive Loop Filter Architecture With Optimized Memory for VVC;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-11
3. The Optimization of Adaptive Loop Filter Based on the Reduction of the Filter Sets;2023 International Conference on Ubiquitous Communication (Ucom);2023-07-07
4. Efficient HW Design of Adaptive Loop Filter for 4k ASIC VVC Encoder;2022 Picture Coding Symposium (PCS);2022-12-07
5. Editorial Real-Time Implementation of VVC Standard for Consumer Electronic Devices;IEEE Transactions on Consumer Electronics;2022-05
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