FPGA Implementation of PRESENT Block Cypher with Optimised Substitution Box
Author:
Affiliation:
1. University of Kashmir,Department of Electronics & Instrumentation Technology,Srinagar,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10009016/10009051/10009366.pdf?arnumber=10009366
Reference18 articles.
1. Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers
2. Compact FPGA implementation of PRESENT with Boolean S-Box
3. Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher
4. Lightweight Hardware Architectures for the Present Cipher in FPGA
5. High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers
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