Configuration compression for the Xilinx XC6200 FPGA
Author:
Publisher
IEEE Comput. Soc
Link
http://xplorestaging.ieee.org/ielx4/5734/15334/00707891.pdf?arnumber=707891
Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. High performance decoding aware FPGA bit-stream compression using RG codes;Cluster Computing;2018-03-31
2. Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-10
3. TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs;Microprocessors and Microsystems;2015-11
4. Morphable Compression Architecture for Efficient Configuration in CGRAs;2014 17th Euromicro Conference on Digital System Design;2014-08
5. Test compression for dynamically reconfigurable processors;ACM Transactions on Reconfigurable Technology and Systems;2011-12
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