Memory Pooling With CXL-Reference-Cited by-同舟云学术

Memory Pooling With CXL

Author:

Gouk Donghyun¹^ORCID,Kwon Miryeong¹^ORCID,Bae Hanyeoreum¹,Lee Sangwon²,Jung Myoungsoo²^ORCID

Affiliation:

1. KAIST, Daejeon, South Korea

2. KAIST and Panmnesia, Daejeon, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

Reference14 articles.

1. Direct access, high-performance memory disaggregation with DirectCXL;gouk;Proc USENIX Annu Tech Conf,2022

2. TPP: Transparent page placement for CXL-enabled tiered memory;maruf,2022

4. Inductive representation learning on large graphs;hamilton;Proc Neural Inf Process Syst,2017

5. Semi-supervised classification with graph convolutional networks;welling;Proc Int Conf Learn Representations,2016

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