Author:
Pandey Kumar Sambhav,B Dinesh Kumar,Goel Neeraj,Shrimali Hitesh
Cited by
13 articles.
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1. Performance of Well-Organized VLSI Architecture for Three Operand Binary Adder;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17
2. Design and Implementation of Energy Efficient Approximate Three Operand Binary Adders;Lecture Notes in Networks and Systems;2024
3. Low Power Multiplier using SPST based on Kogge Stone Adder;2023 International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2023-04-29
4. VLSI Architectures of Three Operand Binary Adders;2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS);2023-04-19
5. Area and Delay Efficient Hybrid Prefix Adders for Residue Number System Applications;2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT);2023-04-08